Power-oriented checkability of matrix and pipeline circuits in FPGA-based digital components of safety-related systems

Abstract

The checkability of the circuits is considered as a necessary condition for ensuring functional safety for safety-related systems based on the use of fault-tolerant solutions. The features of logical checkability, which is essential for testing, testable design and on-line testing of digital components of safety-related systems, are analyzed. Logical checkability is represented as structural, structurally functional and dual-mode, typical for critical applications. The problem of hidden faults is noted, which shows the lack of dual-mode checkability in the design of digital components based on matrix structures. The resource-based approach identifies this problem as a growth problem, the solution of which requires the reduction of matrix structures. The maximum reduction is achieved in bitwise pipelines. The limitations of logical checkability are shown in solving the problem of hidden faults under the conditions of the dominance of matrix structures and in the monitoring of faults in chains of the common signals. The success of green technologies in FPGA design created the conditions for the development of power-oriented checkability, which significantly complements the logical checkability of the circuits. An analytical evaluation of power-oriented checkability was obtained. The results of power-oriented checkability evaluation experiments are shown to be important for faults in chains of the common signals. Experiments were carried out for matrix and bitwise pipeline circuits using the example of multipliers of numbers. A comparative analysis of the results obtained.