Аннотация:
PGA-designing (Field Programmable Gate Array) with LUT-oriented (Look-Up Table) architecture enjoys well-deserved recognition in the
field of safety-related applications, where important tasks are solved to ensure
the functional safety of high-risk objects to prevent accidents. These tasks are
assigned to safety-related systems, which are the development of ordinary computers with the division of operating mode into normal and emergency ones and
increased requirements for functional safety provided using fault-tolerant solutions. Under these conditions, FPGA designing encounters the problem of hidden faults that can accumulate in memory bits of LUT units in normal mode
and reduce the fault tolerance of the FPGA project with the beginning of the
most responsible emergency mode. This problem is due to the limited checka-
bility of FPGA projects, which is due to memory bits addressed only in emergency mode. The method of improving the checkability of FPGA projects based
on the version redundancy of their program codes is proposed. The work of
FPGA projects is organized with a periodic change of program code versions
for addressing in normal mode to all used memory bits. The method is shown in
the example of the FPGA project designed for the iterative array multiplier,
where it determines all versions of the program code and selects their minimum
number to maximize the checkability of the project.
