Аннотация:
The paper focuses on the study of the checkability of digital circuits in relation to FPGA
(Field Programmable Gate Array) components of safety-related systems that serve high-risk
facilities, maintaining their functional safety in synergy with its own. Functional safety
breaches are associated with failures that stimulate the use of fault-tolerant solutions.
However, the possibilities of these solutions are limited by the number of failures which can
be countered. As a result, functional safety, based only on circuit fault tolerance, faces the
problem of multiple failures. This problem manifests itself in the example of hidden faults,
which can be accumulated in significant quantities during extended normal operation of the
system. The multiple manifestations of these faults in emergency mode call into question the
fail-safety of fault-tolerant circuits, including FPGA components, which can accumulate
faults in the memory of the LUT units. Ensuring the fail-safety of circuits requires taking into
account their checkability, which depends on the data arriving at the inputs of the circuit in
normal and emergency modes. A method for assessing checkability, which is important for
the fail-safety of FPGA components, is proposed. Checkability is assessed on real input data,
the change of which often extends only over a part of the range of values related to the
normal functioning of the system. The method makes it possible to evaluate the change in the
checkability of the circuit depending on the change in its input data.
