Checkability important for fail-safety of FPGA-based components in critical systems

Abstract

The paper is devoted to the analysis of FPGA (Field Programmable Gate Array) components with LUT-oriented (Look-Up Table) architecture for safety-related systems that are aimed at ensuring the functional safety of high-risk facilities in conjunction with their own safety. Functional safety is based on the use of fault-tolerant solutions, for which multiple failures are the biggest challenge. One of the sources of such failures is associated with the problem of hidden faults that can accumulate in digital circuits during a long normal mode and manifest themselves in a decrease or loss of the fault tolerance of these circuits in the most responsible emergency mode. The accumulation of faults occurs in connection with the limited checkability of digital circuits in normal mode and due to the change in checkability with the beginning of the emergency mode. The lack of checkability of the FPGA components, which manifests itself in the memory of the LUT units, does not allow the faulttolerant circuit to be transformed into a fail-safe one. A method for assessing the checkability of circuits with LUT-oriented architecture in the part that ensures the fail-safety of a faulttolerant solution is proposed. Two sets of memory LUT bits are determined that are important to the circuit in terms of providing fail-safety and its violation, respectively. The program implementation of the method demonstrates its capabilities on the example of an iterative array multiplier implemented in an FPGA project.