Embedding the Digital Watermarks into FPGA-Projects Containing the Adaptive Logic Modules

Abstract

The given paper deals with the problem of embedding the digital watermarks into program code of the FPGA chips. A digital watermark gives the possibility to place the extra information hidden from an outside surveillance in the program code FPGA. This can provide the integrity monitoring and monitoring of usage of FPGA program code processes. The matter is that the existing methods of the digital watermark embedding are focused on FPGA, in which basic logic elements contain only a programmable calculating unit LUT and programmable flip-flop. The adaptation of method of the digital watermark embedding to FPGA chips, which have dedicated hard full adders in the composition of basic logic elements, is offered. The analysis of the proposed method implementation has been carried out. It turns out that the usage of the offered method increases the embedded digital watermark size.