This paper is devoted to development of a method of the results preparation for development of the digital circuits carrying out addition operation which is basic for arithmetic calculations. The method of the results preparation is widely presented in information technologies. By this method all libraries, including libraries of the software and IP-core libraries are organized. The method gained development in design of the fixed-point adders on FPGA with the LUT-oriented architecture for the organization of operation of the logical elements in the dynamic arithmetic mode with the accelerated propagation of carry signal. We offer development of a method of the results preparation for realization of arithmetic addition of the floating-point numbers which plays an important role in processing of approximate data. Floating-point addition operates with the numbers presented by mantissas and exponents. The method of the results preparation provides paralleling of processing the exponents and mantissas which are traditionally carried out consistently: at first operations with exponents determine shift sizes, and then the shift of mantissas is executed. Parallelization of processes is carried out by preparation of a set of the sums for various options of their relative positioning after shift. The size of shift is used for the choice of the sum corresponding to it from a set of the prepared sums. The offered method is estimated by time of operation performance in floating-point addition and complexity of its realization for decisions with various level of circuit parallelism.
