Аннотация:
The use of lossless compression in the application specificcomputersprovides such advantages as minimizedamount of memory, increased bandwidth of interfaces, reducedenergy consumption, and improvedself-testing systems. The article discusses known algorithms of lossless compression with the aim of choosing the most suitable one for implementation in a hardware-software decompressor. Among them, the Lempel-Ziv-Welch (LZW)algorithm makes it possible to perform the associative memory of the decompressor dictionary in the simplest way by using the sequential reading the symbols of the decompressed word. The analysis of the existing hardware implementations of the decompressors showed that the main goal in their development was to increase the bandwidth at the expense of increasing hardware costs and limited functionality. It is proposed to implement the LZW decompressor in a hardware modulebased on a microprocessor core with a specialized instruction set. For this, a processor core with a stack architecture was selected, which is developed by the authors for the tasks of the filegrammaranalyzing. Additional memory block for thedictionary storing and an input buffer which converts the byte stream of the packed file into a sequence of unpacked codes are added to it. The processor core instruction set isadjusted to both speed up decompression and reduce hardware costs. The decompressor is described bythe Very high-speedintegral circuit Hardware Description Language and is implemented in a fieldprogramable gate array (FPGA). At a clock frequency of up to two hundred megahertz,the average throughputof the decompressor is more than ten megabytes per second. Because ofthe hardware and software implementation, an LZW decompressor is developed, which has approximately the same hardware costs as that of the hardware decompressor andhas a lower bandwidth at the costs offlexibility, multifunctionality, which is provided by the processor core software. In particular, a decompressor of the GraphicInterchangeFormat files is implemented on the basis of this device in FPGA for the application of dynamic visualization of patterns on the embedded systemdisplay
