Development of checkability in FPGA components of safety-related systems

Abstract

The paper is dedicated to the development of FPGA-designing (Field Programmable Gate Array) components for safety-related systems as an important direction in improving the functional safety of high-risk facilities and the control systems themselves in order to counter accidents and their consequences. The critical application of the computer system diversifies its operating mode into normal and emergency, as well as increases the requirements for fault tolerance of circuits as a basis for functional safety. Fault- tolerant solutions do not become fail-safe in conditions of insufficient checkability, which is inherent in modern safety-related systems and manifests itself in the problem of hidden faults. They can accumulate during normal mode and eliminate fault tolerance in emergency mode. FPGA projects with LUT-oriented (Look-Up Table) architecture inherit this problem in the LUT memory, which is used only in emergency mode. The proposed method develops the FPGA components’ checkability by using the version redundancy of their program code. Periodic change of the program code version in normal mode allows to address the memory, which was previously used only with the transition to emergency mode. All versions support the component’s FPGA functionality while maintaining its hardware implementation. The method evaluates the controllability and observability of the LUT memory and determines versions that increase its checkability.