An Approach to Stego-Container Organization in FPGA Systems for Approximate Data Processing

Abstract

The paper is devoted to the development of steganographic approaches to checking the integrity of an FPGA (Field Programmable Gate Array) system based on preserving the basic functionality of stego containers and hiding both the hash sum and other control information as well as the very fact of their existence. The program code of an FPGA project with a LUToriented (Look-Up Table) architecture is proposed to be used to organize stego-containers when performing approximate calculations in floating-point formats. The development of this approach is based on the progressive dominance of hardware support in the processing of approximate data and the orientation of modern CAD systems to provide library circuit solutions for performing complete arithmetic operations. Floating-point formats round the computed result to the size of the operand. The use of these formats in FPGA systems creates structural redundancy in the schemes for implementing complete arithmetic operations and thus eliminates the influence of a number of LUTs on the rounded result. The code stored in these LUT units can be used to organize stego containers. A TCL-application developed for this purpose generates a circuit description for an analyzed FPGA system with a LUToriented architecture. The following application uses the resulting description to evaluate the effect of LUT units on the bits of the calculated result. Experiments carried out for iterative array multipliers implemented in FPGA projects made it possible to estimate the volume of stego-containers that can be used when performing approximate calculations in floating-point formats.