Checkable FPGA Design: Energy Consumption, Throughput and Trustworthiness

Abstract

Green FPGA design represented in the directions of energy efficiency and safety which are tightly connected in the areas of critical application is considered. The array structures that are traditionally used in digital components of safety-related systems, reduce a checkability of circuits, creating a problem of the hidden faults which can be accumulated in a normal mode and reduce the fault tolerance of the circuit and safety of system in the emergency mode. Soft and cardinal ways of array structure reduction are offered. The soft way consists in development of the truncated arithmetical operations implementing into reduced array structures. The cardinal way consists in paralleling of calculations in serial codes with the use of bitwise pipelines. The comparative analysis in complexity, throughput and energy consumption of the iterative array and bitwise pipeline multiplier is executed experimentally with use of Altera Quartus II. Methods of on-line testing in checking of mantissas by inequalities are developed for the truncated operations. A method of increase in safety of FPGA circuits in opposition to accumulation of the hidden faults and a method of monitoring in integrity of FPGA project are suggested on the basis the program code diversity use.